As is well known, a semiconductor non-volatile memory structure comprises a matrix array of memory cells, each formed by a MOS transistor having a floating gate terminal formed above its channel region. Each cell also comprises a second terminal, called the control gate, which is driven by means of suitable control voltages. Other terminals of the transistor are known as drain, source and body terminals.
A non-volatile memory integrated on a semiconductor comprises an array of cells in a matrix layout of rows or word lines and columns or bit lines. The cells in one word line share the electric line which drives their respective control gates, and the cells in one bit line have their drain terminals in common. Through the application of suitable voltage values to the terminals of the cell, the amount of charge present in the floating gate can be changed, thereby allowing the transistor to take either of two logic states.
The floating gate has a high impedance toward any other terminals of the cell, and the charge stored therein can be retained for an indefinite length of time, even after the power supply to the circuit in which it is connected is disconnected. Thus, the cell can function as a non-volatile memory. The operation whereby charge is stored into the floating gate is called a "programming phase."
Each individual cell is programmed by a hot electron injection process whereby electrons can be trapped within the floating gate as the control gate is put in contact with approximately 12 volts, with the source terminal being connected to ground and the drain terminal held at a drain voltage of about 5.5 volts. It is a well-recognized fact that non-volatile memory cells, particularly those of the FLASH type, require accurate control of the drain voltage applied to the bit line during the programming phase. Such a voltage should, in fact, satisfy the following set of conditions:
it should be sufficiently high to permit fast cell programming; PA1 at the same time, it should be sufficiently low to avoid the inception of the so-called "soft-erasing" phenomenon, whereby the cell would be partially erased or the cell characteristics degrade in use; and PA1 it should be adapted to avoid, for reliability reasons, triggering the phenomenon known as the "parasitic bipolar" phenomenon.
The optimum range for the drain voltage is usually a fairly narrow one, typically from 5 to 6 volts. It should be further noted that the above-listed conditions may vary with the manufacturing process, and especially with the length of the memory cell. Manufacturing processes do introduce variations in the dimensions of the cell, specifically in those of the polysilicon layers, which affect the value of the drain voltage to be applied.
On the whole, the above considerations indicate that the storage circuit should be provided with a voltage generator which is specially effective and accurate in supplying the bit line with the appropriate drain voltage during the programming phase.
The prior art has already proposed solutions directed to fill this demand. One known solution is based on the principle that basically two voltages are supplied to the storage circuit from outside, namely a supply voltage Vcc of 5 volts and a programming voltage Vpp of 12 volts. It has been common practice to provide the drain voltage by dividing the programming voltage Vpp. In this way, a drain voltage can be obtained which is fairly stable versus temperature and the circuit manufacturing process parameters, although it may vary by .+-.5% with the programming voltage Vpp. However, during a programming phase the threshold voltage of the cell gradually tends to rise, and the current drawn by the cell decreases over time. Through the resistive divider, the voltage is generated on the basis of a mean value of the programming current, and this regulation cannot give consistently good results.
A second known solution is described in U.S. Pat. No. 5,263,000, whereby the drain voltage is supplied from a voltage booster which is fed the supply voltage Vcc of 5 volts and includes a charge pump circuit controlled by a clock signal. Even this prior approach is not devoid of shortcomings. The output stage, when so configured, has proved high in current consumption, presumably because of a current loss occurring between the booster output and ground. Furthermore, the charge pump circuit, which supplies within one half-period the boosted voltage to an output node of the generator, will leave that node "floating" during the next half-period.
A third known solution proposes to use a clock signal with linear delay propagation to control a plurality of charge pump circuits. However, this approach cannot ensure an appropriate phase shift of the charge pump circuits, and with it, proper performance of the voltage generator.
In addition, the charge pump circuits utilized in the prior art have no limitation on the rise of the internal voltages, which may result in malfunctions of the charge pumps incorporated to the generator.